The present disclosure relates to a nonvolatile semiconductor memory device having a memory array in which nonvolatile memory cells are arranged using a virtual ground.
Flash electrically erasable nonvolatile semiconductor memory devices have a feature that stored information is not lost even in a power-off state. Various methods have been proposed on how to form an array of memory cells in a nonvolatile semiconductor memory device. Among such methods, there is a method where metal oxide nitride oxide silicon (MONOS) memory cells that store information by local injection of charge are arranged using a virtual ground, to constitute a memory array. This method has recently attracted attention because it is advantageous in reducing the layout area and is simple in structure and thus easy in fabrication.
In MONOS memory cells, two-bit information can be stored in one memory cell by injecting charge locally into portions of a MONOS film near two bit lines connected to the memory cell (see U.S. Pat. No. 5,768,192).
FIG. 4 is a cross-sectional view showing a configuration of a MONOS memory cell. The MONOS memory cell shown in FIG. 4 includes a gate 401 connected to a word line, n-type diffusion layers 402 and 403 connected to bit lines, and a thin film 404 of a MONOS structure placed between the gate 401 and a p-type substrate 407. The reference characters A1 and A2 respectively denote charge injection areas as portions of the MONOS thin film 404 near the diffusion layers 402 and 403, into which charge is injected for storing information.
The memory cell of FIG. 4 can store two-bit information using the charge injection areas A1 and A2. The program operation of injecting charge into the charge injection area A1 near the diffusion layer 402 is performed in the following manner, for example. A voltage of 9 V is applied to the gate 401 of the memory cell via the word line, 5 V is applied to the diffusion layer 402 via the first bit line, and the diffusion layer 403 is fixed at the ground potential via the second bit line. With this voltage application, hot electrons generated by a current flowing through the channel are injected into the charge injection area A1. Similarly, the program operation of injecting charge into the charge injection area A2 near the diffusion layer 403 is performed, for example, by applying 9 V to the gate 401, fixing the diffusion layer 402 at the ground potential, and applying 5 V to the diffusion layer 403. In other words, the voltage states of the diffusion layers 402 and 403 are interchanged with each other. In this way, hot electrons generated by a current flowing through the channel is injected into the charge injection area A2.